A latch may be a level-triggered circuit that may drive an output terminal according to one of multiple stable output states. For example, a latch may drive an output terminal to match a voltage level of an input terminal while an input clock is logic level HIGH. The latch may then maintain the voltage level at the output terminal while the input clock is logic level LOW, independent of the voltage level of the input terminal.
A latch may become unstable or metastable and generate a voltage that is between defined stable states for the latch. The latch may become metastable for a number of reasons. For example, the latch may become metastable if a set up time is violated. The latch may be metastable if a hold time is violated. Various factors may aggravate latch metastability, such as low temperature conditions (e.g., 0° C.), low voltage conditions (e.g., 50% of maximum VDD), or other slow semiconductor process corners. Without assistance, a latch may remain metastable indefinitely, or until random noise causes the latch to favor one stable state over another.